Computing machines



Oct. 17, 1961 R. P. B. YANDELL COMPUTING MACHINES Filed Sept. 24, 1956 6 Sheets-Sheet 1 Pack 5 Track Oct. 17, 1961 R. P. B. YANDELL 3,004,706

COMPUTING MACHINES Filed Sept. 24, 1956 6 Sheets-Sheet 2 cm F/ a/ IVOZ 5 Fig. 2.

x iissddddddd m ZZZma imp/ mf/cance Inventor Oct. 17, 1961 v YANDELL 3,004,706

COMPUTING MACHINES Filed Sept. 24, 1956 6 Sheets-Sheet 3 A 70 BA? 5/ HT H92 A 25 8A4 :95 5/ M8 M70 BA8 84 Fa-p2 Zili 6 Sheets-Sheet 5 Filed Sept. 24, 1956 w. Fr?

\ :t In uentor Wan 4497. 3 )M/UE L QQQ mm N mm #3 6 Sheets-Sheet 6 HT LT "00 Inventor R. P. B. YANDELL COMPUTING MACHINES Oct. 17, 1961 Filed Sept. 24, 1956 United States Patent Claims priority, application Great Britain Oct. 25, 1955 Claims. (Cl. 235170) This invention relates to Computing machines and in particular to electrically operated adding apparatus for use therein. I I v s As is well understood, the binary system of calculating affords certain advantages but involves the use of a considerable amount of coding circuitry to/obtain the information in binary form and further circuitry to con- ;Iert the binary answer to the requisite decimal or Sterling orm.

It is a main object of the present invention to provide a relatively simple apparatus whereby decimal or Sterling amounts to be added can be transmitted to a coded binary adder for addition thereby and the answer obtained according to the scale of notation of the input digits to the adder. v

According to the present invention there is provided electrical computing apparatus comprising a coded binary parallel adder, means'to read two parallel binary coded digits simultaneously'from store and to transmit them to said adder, a correction codingcircuit including cor.- rection coding gates to which parallel binary outputs from the adder representative of the binary sum of the binary coded digits are applied, and notation control means operable under control of a scale of notation determining indication read from store and representative of the scale of notation of the binary coded digits to apply a radix determining pulse to said gates thereby to condition said gates so that on application thereto of parallel binary outputs from the adder said gates produce parallel outputs representative of a binary coded digit having the 'same radix as that of the digits read from the store and as necessary a carry for entry into the adder.

In order that the invention may be more clearly understood, oneembodiment thereof will now be described, by way of example, with reference to the accompanying drawings, in which:

FIGURE 1 is an elevation of a portion of a magnetic data-storage drum,

FIGURE. 2 illustrates the arrangement of data-receiving sections for a track extending round the drum at right-angles to the axis of rotation thereof,

FIGURE 3 illustrates the manner of recording data on a data-receiving section of the drum,

' FIGURE 4 is a block diagram of computing apparatus according to the invention,

FIGURE 5 is a circuit diagram of digit input gates and a Sterlingcontrol circuit forming a part of a notation control unit,

FIGURE 6 is a diagram of a scale-often control circuit and of a pence and tens-of-shillings control circuits also forming part of the notation control unit,

FIGURE 7 is a diagram ofa binary adder, being 'one of four such adders employed as a unit for effecting addition of digits from the input gates of FIGURE 5,

, 3,004,706 v Patented Oct. 1 7, 1961 FIGURE 8 illustrates a correction coding circuit by which binary digits from the adding unit are coded according to the scale-of-notation of the digits passed by theinputgates to the adding unit,

FIGURE 9 is a carry delay circuit by which a carry pulse emanating from the correction coding circuit'is delayed before being entered into the adding'unit, and

FIGURE '10 is a waveform diagram illustrating the mode of operation of the carry delay circuit.

In the following description there is, for convenience, described 'the application of the invention to a computing-machine in which numbers to be added are stored, in known manner, on a drum D, FIGURES 1 and 2 having a magnetisable peripheral surface and arranged for continuous rotation about its longitudinal axis. It is to be understood,.however, that other forms of number storage may, if desired, be employed. 1

Referring to FIGURES 1 to 3, the drum storage will I be breifly described in-so-far as knowledge of the mode of operation thereof is necessary to the understanding of the present invention. Numbers to be added, and the terms added and adde'rf when used herein are deemed to include the op .eration of subtractionby the addition of complements, are stored on predetermined areas of the drum D extending circumferentially round the drum at right-angles to the axis of rotation thereofand being spaced apart axially on the drum. FIGURE 1 illustrates four such areas or tracks each of which consists of four bands to which, as indicated in FIGURES 1 and 3, there is allocated respectively the significance 1, 2, 4,8 to permit the recording of digits on the track according to the l, 2, 4, 8 code. a I

Each track, as indicated in FIGURES 1 and 2, is to suit the electronic timing, assumed to be divided into forty track locations which, as indicated in FIGURE 2, pass continuously in succession under data-recounting means shown as write heads WH and read heads RH, one for each band of a track. Each track location is, as

illustrated in FIGURE 3 assumed to be sub-divided into twenty sub-locations each of which passes beneath write heads and read heads for a period of time during which digit times pulses DTl to DT20, as appropriate, permit figures coded according to the 1, 2, 4, 8 code to be written on or read from a track location. The track location illustrated in FIGURE 3 is assumed to have the amount 96. 15. 11d. recorded thereon by magnetiscd areas MA, and the order of the sublocations is such that an amount is recorded only in the sub-locations DT3 to DT18, the sub-locations DTI, DT2, DT19 and DT20 having other purposes of which DTZ is a reading time during which there can be read a notation determining indication indicative of the kind of number recorded in sublocations DT3 to DT18. Thus, if as in FIGURE 3, the number or amount ispositivc Sterling no recording is made in DT2 but if the amount is negative Sterling a notation determining indication is recorded in the 1 band in sub-location DT2. Should the number be positive decimal a notation determining indication is made in sub-location DTZ in the 8 band, and if the number made in sub-location DT2 in each of the 1 and 8" 3 bands. A recording in the 1 band of DT2 is used to control a digit complementer, forming no part of the present invention and not shown or described herein, whereby there is passed to the adder the complements of the digits read from sub-locations DT3 to DT18 following the reading of a recording in the 1 band of DT2. If, however, the number recorded in the track location is already in the complemental form thereof this is indicated by a recording in the sub-location DT19 as described below.

As can be seen from FIGURE 2 numbers to be added are read from. the drum and. are. transmitted as, pulses along-highwaysiHl andiHZ, as; appropriate, each highway consisting of four binanyeoded lines, one {or each. track band, shown in FIGURES 4; and 5: as H11, H12, H14, H18: and H21, H22, H24, H28. An answer to be recorded. on the drum. is transmitted to the write heads along a highway H3, FIGURE, 2, which consists of four binary coded lines H31, H32, H34, H38, FIG- URES 4 and 8; arrangement is such that the digits of an amount are read serially from storage, commencing with digit of lowest denominational order, are passed'to. a coded binary adder comprising binary adders BA1, BAZ, BA4, BA8, FIGURE. 4, and the. answer is recorded on the drum inthe. same digital order. Wh n two. numbers areto' be. added thedigitsof'like derto lirnt tional order are read concurrently from, store.

The sub-location BT19 iszused; to, indicate either the sign of. a number record d: in track location or h the number recorded is in error due to it exceeding the storage capacity. Thus, if the number is positive there will be no indication in sub-locationv D119. If, however, the number recorded is negative it will, as stated above, be in its complementary form and a sign digit 9 will be rewrded in. sub-locati n BT19 in bands 1 and 8 thereof. Should there be, recorded in sublocation BT19 either 1 or 8 alone this will indicate that the number recorded in the track location is, due to overcapacity, incorrect. Examples of these conditions are as follows;

EX MP E 2 Negative result: 12340000009=543210DQ0EQQBIQOODO rr DT D'I DT DT Dir. DT D'I DT DT 131* 0-1 2 a 4 .o .0. 0.0: 0.0 9,4 -s- 1 o.- o o o 0 0 9ss 0'1900000 EXAMPLE 3 Bositlverovercepaciiy: 5532199 K i-654320000il=1197530t1000 in o D'l or or: mini or or :D Dr 19 1s 17 1s '15 14 is 12-11 9 0 5 43 2 too 0- 0 0 in exts. 4 2 ,0 -0 .-0 o 1 o 1- "5 5 0. o--=-o. .0 0.

Referring now, to FIGURES 4 to, 10,, the numbers to e. added pass alongthe highways H1 and H2, line.s H11; H12, H14, H18, H21, H22, H24, H28, FIGURES tend 5, to. digit input control gates HCG'l and H662 which permit the passage of pulses only during digit times ET 3 to BT19 and are arranged to stop the passage ofa decimal notation indicating pulse, if present, during digit time DT2. To this end gates HCGl have a pulse CPI, FIGURE. 5, applied thereto during digit time DIfi-to BT19. sov that they n only passv pulses during, these digit times. The gates HCGZ are maintainedfil'QSdd 92;: cept, during, digit times DT3 to BT19 by a pulse appli d at, one which is down in potential during di t imes D11, TZ n D ZQ- When addition is eing effected a p se s applied. at CP3 but the. function of this pulse is not concerned with the functioning ofvthe. apparatus according to the present invention. Thus if during digit ti fisDT3 to BT19 ulses are assed t gates HCGI and HCGZ along lines H11, H12, H14, H18, 1121,1122, H24 or H23 they will pass through gates I-ICG 1 and HCG2 as binary pulses A and B respectively and pass throughpnlse shapers PS1 to the adder.

Any suitable form of coded binary adder unit may be used but as herein described it is assumed. that the unit is of, the kind from Which can be obtained hat. are known as netted outputs from the additionofbinary inputs A, B, C where C is a binary carry input, A number of such suitable formsof adder unit are, known and it is to be understood that that described below with reference to FIGURES 4 and 7 is mentioned only by way of example and to facilitate the understanding of the present invention.

As illustrated in FIGURE 4, the adder unit consists of f r binary ad er BA2, A 3A8 e h o which, as shown in FIGURE 7, will receive binary inputs A and B and a binary carry input DC, FIGURE ,9, it the adder is BA1, which may have been created d ing, the next preceding digit time, or C which may have been produced by an adder BA1, BA2 or BA4. As shown in FIGURE 4, the adder BAl is arranged to add binary digits appearing on lines H11, H21 and a carry DC from they next preceding digit time. The added BAZ. adds the binary digit from lines H12, H22 and a carry C from BAI while the addersBA4. and BA8 respectiv ly add the binary digits from lines H14, H24, and carry C from 3A2, and from lines H18, H28 and carry C from 3A4. The outputs from the binary adder unit representing the sum digit coded l, 2, 4, 8, 16 of which the 16 output is the ca ry from HA8, are taken to a correction coding unit CCU, FIGURES 4 and 8, which gives a carry output to BA1 together with a sum digit coded 1, 2, 4 and 8 according to the scale of notation of the digits added from highways H1 and H2. The carry from the correction coding unit CCU is, as described belonw, delayed by one digit time before being added into BAl with the digit of next higher denominational order.

From the foregoing it will be understood that the three inputs to the adder unit consist for BA1 of A, B and DC, and for BA2, BA4 and BAS of A, B and'C, each of which inputs may be I or 0 and the outputs tin: adders, with or without a carry C, are respectively-S1; S2, not .82; S4, not: S4; and S8, not S8; FIGURESA-and the letter S. being common to. the outputs; and being aoomoe representative of the sum'of A, B, C, or combinations thereof. It will also be understood that in each digit time the adder unit adds together two foundigit binary numbers together'with any carry from the next preceding digit time and that the sum from the adder unit is represented 'by a five-digit binary number of which the fifth digit is a carry. It is also to be understood that although there is described herein the use of digits coded according to the 1, 2, 4, 8 code'any other suitable code may be used, for example the 1, 2, 4, 5 code, provided that it wiLl accommodate all digits according to the scale of notation being. employed, in the present instanceboth decimal and Sterling .digits. Examples of the mode of operation are asv follows:

EXAMPLE 5 5+7 =12; addition effected in BT12, Sterling 16 Bits 13x4 BA2 BA1 0 o 1 o 1 0 o 1 1 1 EXAMPLE 6 g 1od.+9d.= 1od.; addition efiected in DT9, Sterling l6 BAS 3A4 BA2/ BA1 0 -1 o 1 0 0 I 1 o o 1 1 o o 1 p 1 )EXAMPIZE 7 4+3=7; addition efieeted any of DT3 to BT18, decimal is I 3A8 BA4 BA2 BA1 I 0 o 1 g o 0 0 0 0 1 1 o a 0 1 1 1 Q 1' The outputs from each adder of the adder unit maybe summarized as shown in Table 1 in which, as already indicated above, A is a binary input'from H1, B isa binaryinput from'HZ, 'C is a carry, and S is the output sum digit in binary form.

Table 1 A B C p S Carry a output I From Table 1 it will be seen that an S output digit is required in each of the four following instances: 1

B, C, not A A, B, C

are achieved by gating, the input potentials A, B, C are passed through pulse shapers PS1, PS2, FIGURES 4 and 7, each ofwhich gives two outputs, FIGURE 7. One

. binary adder there are seven gates BAG corresponding to the seven conditions mentioned above and set out in Table 1. I The outputs from four of the gates BAG are mixed together by connecting them to a single digit output line SDO through four cathode followers CFI sharing the same cathode load CLl. The outputs along line SDO are taken through a pulse shaper PS3 giving outputs in opposite phase and these outputs, being respectively the S and not S outputs to CCU, pass through cathode followers CFZ. The outputs from the gates of the other group of four gates BAG are mixed together by connecting them to a carry output line CO through four cathode followers CF3 sharing the same cathode load (3L2. The outputs along line C0 are taken to the carry input of the next adder or in the case of BA8 through a pulse shaper PS4, FIGURE 4, giving outputs in opposite phase, these outputs being respectively those indicated as 16 and not 16, FIGURES 4 and 8. I

The correction coding unit, FIGURE 8, receives the outputs from the adder unit, which are in binary form, and corrects the coding according to the scale of notation of the two input digits from H1 and H2. In the apparatus herein described, the possible scales of notation are 2 (tens-of-shillings), '10 and 12 (pence) and three notation control circuits SOT, TOC, and PC, FIGURES 4 and 6, appropriate one each to each of these scales of notation are brought into the unit CCU. In each digit time BT3 to DT19 the appropriate one of these notation control circuits will be up in potential. The function of the notation control circuits is illustrated by the following examples:

EXAMPLE 8 12 from the adder unit in DT12 results in 2 in DT12 with a carry to DT13, thus: 01 100 from the adder unit 0010 carry from the correction coding circuit.

EXAMPLE 9 19d. from the adder unit in DT9 results in 7d. in DT9 with a carry to DTIO, thus: 10011 from the adder unit Ol l l carry from the correctioncoding circuit.

EXAMPLE 1o 7 from the adder unit during any DT3 to DT18 gives 7 and no carry, thus: 00111 from the adder unit 0111 from the correction coding circuit. 7 y

The possible outputs from the adder unit and the corresponding outputs required from the correction coding unit CCU whenscale-of-two numbers are being added are shown in the following Table 2.

Table 2 Possible outputs from adder Output from correction coding ber of C (16) 8 4 2 1 p 10/- Carry 8 4 2 1 i 0 0 0 0 0 0 0 0 O O 0 0 0 0 0 1 1 O O 0 0 1 0 0 O l O 2 1 0 0 D 0 0 0 0 1 1 3 1 0 0 0 1 (Maximum output 10/+10/ +carry from shil1ings=1: 10; 0).

The possible outputs from the adder unit and the cor- To obtain the controls from which the said outputs responding outputs required from the correction eoding' "'7 uni CCU when cale-omen. numbers are being a d d are shownin t e fol owing T bl Table 3 L Rossihlc outputs from adder I i 'Decim-al notation J Barry 8 4 ii 2 1 Outputs from correction coding onny s -4 2- tinnitus; not guarantees" r The pos ible outp s from the adder unit. and he corresponding outputsrequiredfrorn he orre iou .oding unit, CCU when s aled-twelve numbers. are being: ad ed are shown; in the iollowiug Table. 4;;

Table 4 a Possible outputs from adder Outputs from correction Number 0.0 'ng ofpencc 7 (Barry 8 4 2 1 (Maximum output 1ld.+11d.+1 carry.=ls. lid).

The notation control cireu'itsare shown in FIGURES and; udjshnuld pulses be present; onlines H18 r H123 during DTZ they will be prevented from. passing through; gates HCGl and H662 but will: pass along lines H 8 H281 to :1 Sterling control cir uit, FIGUREv 5, where they are applied to Sterling control gates SCGl, SCGZ to which a pulse is also applied at SCP during DIZ, the digit time during which pulses along lines H181 and H281 indicate that decimal numbers are to be; added. The outputs from. gates SCGl and SCGZ are mixed and there will be a pulse from this mix only if the numbers about to. be added are decimal numbers. The mix of outputs from gates S661 and SCGZ' is discharged by a pulse DWFI, FIGURES 5 and 10, to give a sharper pulse :to trigger a, flip-flop TCI. The pulse so produced, is used to trigger the anode M of the flip-flop trigger-circuit TCl down in potential atthe end ofdigit time DTZ; and the anode remains down until it is triggered back at the end of digit time BT20 by the back edgeof apulse applied at: While theancd isun in. potential-indies? inghat he numbers to be, added are Stedingnumhers, it h lds p the. pot nt al of l n ,SCZ through cathode follower GF4 and this. gate-conditi ning poteutial outrolsthe Gt e-of-tcn control gates S1 11, S132. and pence and teus-efis il ings on rol g te P-lll. an BIZ, FIGURE 6. Th mix also. resultsv i a imal indication: pulse being passed through a, decimal indication control gate DIQ for mixing, vialine DIGl, in th i lineof H5, t nd: ,.but the. f nction of he decimal indicaiou con rol gat fo ms no p rt of the present invention and no further description relative thereto. be inluded herein- Reierring to :6, the anode: N 011 a flip=flop trigger circuit TC2 is normally maintained upin potential by trigger pulses applied at TF1 and TPZ during digit times DT9 and DT11. Gate-conditioning pulses are applied to TF3 and TF4" during digit times 'DTS' and DT10 respectively. When line 3C2 is up in potential the DWFZ pulses in DTS and DT10 pass through the gates STl and STZ respectively and are mixed, being discharged with the, DWF2 waveform. The back edges of these pulses trigger anode N down by the end-of- DTS and the end of DT10. After anode N has been triggered down it is triggered up again by the back edges oftri'gger pulses applied at TPl and TF2.

The scale-of-ten. control, anode N, is therefore up in potential for the whole of a period of digit times DTI t0 0i l n S rl ng numbers are. bein added, except for the periods of digit times DT9 and: DT11, which are the only digit times that the digits to be added are not in the scale-of-ten. When the numbers to be added are wholly decimal numbers the gates STland 5T2 remain closed due to the triggering of anode M as described above and accordingly the potential of anode N remains up for the whole of digit timesDTl to DT20. The scaleof-ten potential on line SOT, FIGURES 6 and 8, is Passed through cathode follower. Q55 to contro h coding of scale-of-ten digits issuing in binary form frompthe adder unit.

During the addition of Sterling numbers, the pence control potential is raised during digit time DT9 when the scale-of-ten potential is down, and the tens-of-shillings control potential is raised during digit time DT11 when the scale'of-ten potential is down. This is effected by gate-conditioning pulses applied at TP6- and/I1 5, FIG- URE 6 duringdigit times DT9 and DT11 to the pence control line PC and the tenseot-shillings control line through gates PTZ and F11. The outputs from these gates are coupled to the grids of cathode followersCFfi, CF7 via capacitors CA, the level of the cathode follower grids being restored to the required lower potential by a restore potential appliedat RP, FIGURE 6.

Each group of gating potentials taken into the correction coding unit CCU, FIGURE 8 is passed to positive coincidence correction coding gates PCG andthe outputs from the gates are mixed, using cathode follower load mixes CFM, of the kind described above with reference to FIGURE, 7 to obtain coded outputs, as appropriate, along the lines H31, H32, H34, and H38 and a carry CC to BAI.

The gates PCG may be ofany suitable form which will give an output on the application thereto, of Pulses from the adder and from the notation control means, but in the preferred form thereof the gates, as can be'seen from FIGURE 8 are connected to a high tension line HT and to a line DWF2 which latter line is provided to remove spurious pulses from the. outputs of the gates and goes up in potential during each digit time DT for an interval of time as indicated in FIGURE 10. Accordingly, the potential on line DWFZ conditions each of the gates PCG so that,.if while the gates are so conditioned, one of the gates also receives pulses, as appropriate, from the adder unit and from the notation control means an output pass: through the gate. For eaamnl iiifz when the seeond-g t tmmthe left, as view d inFIGURE 8 is conditioned there are applied th'ereto pulses S2, NOT S8, NOT@16, from the adder unit and SOT from the notation control means the gate will pass an output to line H32 representative or coded decimal digit 2. Should .there also be pulses S4, NOT 88, NOT '16, applied to the sixth gate from the left of FIGURE 8 then there will also be an output fromfthat gate to line H34 and the two outputs will be repres'entativeyof coded decimal digit 6. The full range of outputs from the correction coding circuit and the significance thereof is shown in tabular form in Table 5.

Pence. Decimal, or pence. Decimal.

Pence.

- Decimal, or pence.

Decimal.

Pence.

OO= Garry- Decimal, or pence. OO=Oarry Decimal, or pence. CC=Carry Decimal O G Carry 'lensbf-shilliugs. I,

From the immediately preceding description it will be understood that correction codingcircuit includes gates which are operable on the application thereto of a notation determining pulse and of pulses from a coded binary adder to cause outputs from the gates representative of a coded digit according to a notationas determined by the notation determining pulse and as necessary a carry for entry into the adder.

It will be understood that because the digits are ontered serially the carry CC must be applied to the adder BAl during the digit time next succeeding that in which it is created. To ensure that the carry CC is applied at the appropriate time there is provided a carry delay circuit, FIGURE 9, consisting of two flip-flop trigger circuits TC3 and TC4. The potential of anode P of TC3 triggers TC4 and the potential of anode W of TC4 is the delayed carry. The wave-forms, FIGURE 10, illustrate the operation of the delay circuit. The clock pulses CP, negative anti-clock pulses NCP, FIGURE 10, pulses DWFI and DWF2 are produced, in any suitable manner not shown, in every digit time (DT) in synchronism with the drum D.

The potential of anode P is normally maintained down by the negative anti-clock pulse NCP triggering the flipflop TC3, and the potential of anode W is maintained down by the DWF2 pulses triggering the flip-flop TC4. If there is a carry during the first DT shown in FIGURE 10 this is applied to a delay unit gate DUG to gate the clock pulse CP to the flip-flop TC3 thus triggering the potential of anode P up on its back edge. The potential of P is brought down again by the negative-going edge of the negative anti-clock pulse NCP at the beginning of the next succeeding digit time DT. Anode P going down in potential triggers up anode W and this remains up until the back edge of the DWF2 pulse in said next succeeding digit time. The up potential of anode W is the delayed carry and is passed through a cathode follower CF8, FIGURE 9, to a carry gate DCG to be gated with a carry-gating pulse applied at DCP during digit times DT3 to DT19 thus limiting the output from the delay circuit to the number digit times DT3 to DT18 and to the sign digit DT19. The output from the gate DCG passes through a cathode follower CF9 and is taken as a carry pulse DC FIGURE 4, through the pulse shaper ,10 PS2 to the input of adder HA1. 1 Accordingly, the carry indicated in the first of the digit times, FIGURE 10, is added in during the next succeeding digit time.

In the foregoing description there has been described an apparatus in which digits to be added are entered serially in ascending denominational order and this form of apparatus is that which is preferred as by reason thereof the apparatus is compact and relatively economical to'produce. It will be understood, however, that if desired apparatus of the kind described may be used for the paralleladdition of digits byproviding a sutficient number, one for each denomination, of sets of the apparatus. When addition is effected in parallel it will be understood that a carry from one correction coding unit will be efiected into the adder unit of next higher denomination and the carry delay circuits will not be employed.

It will be understood that, if desired, instead of the notation-determining pulses being, as described above,

storedwith the numbers a change in notation irom Sterling todec'imal, or vice'versa, could be programmed, in which event the trigger pulse to the flip-flop TCl, FIG- URE 5 would be obtained from a programme decoding unit. Alternatively, a Decimal/Sterling indication could be givenby means of a manually operable switch which when set Sterling would connect the line SCZ, FIGURE 6 to a suitable potential, and which when set to Decimal would connect the line $02 to a suitable lower potential.

1. Electrical computing apparatus comprising a store for numbers in different scales 'of notation each number being preceded by a scale-of-notation indication and each digit of the numbers being represented in a parallel binary code, a parallel binary coded adder having a plurality of orders each order having an output, means for simultaneously reading two numbers serially from the store for addition by said adder, notation control means connected to the store and arranged to store said scale-of-notation indication during the addition of the numbers, a number of radix lines providing outputs from said notation control meanseach radix line being appropriate to a different radix of said digits and the notation control means being operable during reading of the numbers from the store to energize the appropriate radix line for each pair of digits as they are read, a plurality of correction coding gates having inputs connected to said adder outputs, output lines corresponding to said parallel binary code orders connected to said gates and including a carry line connected to the adder, the correction coding gates includ ing a gate for each parallel binary code order operable to route a binary sum unchanged on to the output lines When'the sum does not exceed the radix, and each radix line being connected to at least one gate of the remaining gates which are each connected to predetermined outputs from the adder so that energization of the radix line appropriate to the digits being added conditions the gates connected to said radix line to cause said gates to recode the binary sum output from the adder when it exceeds the radix to produce a corrected binary coded digit in the scale of notation indicated and a carry for addition to the sum of the next digits of the numbers.

2. Apparatus according to claim 1 wherein the notation control means includes a scale-of-ten control circuit, a pence control circuit, and a tens-of-shillings control circuit each to transmit a notation determining pulse to the correction coding gates under control of gate-conditioning pulses and a gate-conditioning potential applied to scaleof-ten control gates and to pence and tens-of-shillings control gates included respectively in said circuits, the gate-conditioning pulses being applied to ensure that the appropriate correction coding gates are conditioned at the times in which decimal digits, pence digits, or tens-ofshillings digits are respectively read from store.

3. Apparatus according to claim 2, wherein said gatecouditioning potential is derived from a Sterling control circuit normally up in potential to apply the gate-condi tioning potential to the scale-of-ten, tothe pence, and to the tens-of shillings control gates said Sterling control circuit being controlled by Sterling control gates conditioned during a time preceding that in which a first digit can be read from store whereby if during said preceding time a decimal control indication is read from store the resultant pulse is applied to the Sterling control gates thereby. to trigger the Sterling control circuit down in potential.

4. Apparatus according to claim 3, wherein the gate- .conditioning potential is derived from one anode of a flip-flop trigger circuit which if the anode is down in potential. at the end of a group of digit reading times is triggered to the condition of being up in potentialby a M1186 applied to; the grid thereof during the last digit reading time of the group.

5. Apparatus according to claim 4, wherein the scaleo-ten notation-d termining pulse is derived from. a flip flop trigger circuit one anode of which is preselected to transmitthe pulse and is normally up in potential and whieh is. triggered down in potential during those digit readingtimesin which pence and tens-of-shillings digits are read from store- 6 Apparatus; according to claim 5,v wherein digits are entered serially into the adder unit and a carry pulse from the correction coding gates is passed to the adder unit. through a carry delay circuit, arranged toenter a carry pulse into the adder unit together with the dig t of next: higher denominational order.

7.. Apparatus. according to claim wh rein. the d lay circuit comprises two flip-flop trigger circuitsthe second of. whisih is. triggered by the first, a delay unitgate through whi h. a. trigger puls is gat d by a carry pulse from th correcti n co ing gates the c rry eing Passed to he grid of the first flip-flop to condition it for resetting by a pulse applied. to the other grid of the flip-flop thereby to'efiect. triggering. of the secon ilp flop and condition acarry gate to pass a carry on application to h ga o acarry-gating pulse.

References Cited in the file of this patent. UNITED STATES PATENTS 2,686,632 Wilkinson Aug. 17, 1954 2,697,549 Hobbs Dec. 21, 1954 2,787,416 Hansen Apr. 2, 1957 2,890,830 woodsefiill "-1 June 16, 1959' FOREIGN; PATENTS 650,685. Great Britain Feb. 28, 1951 678,427 Great Britain Sept. 3, 1952 738,605 Great Britain Oct. 19,1955

OTHER REFERENCES Townsend: Serial Digital Adders for a Variable Radix of Notation, Electronic. Engineering (British), vol. 25, October 1953, pp. 410416 relied on.

Synthesis of Electronic Computing and Control Circuits, Harvard University Press, 1951, pp. 184-1 86 relied Bird: Computing Machines- Input and. Output, Electronic'Engineering, vol. 25, October 1953, pp. 409,- 410. 

